Senior FPGA Engineer. (Location: San Jose, CA)
The Environment:

• You will be a part of dynamic team that works on next generation state of the art test equipment in the field of Ethernet, & IPV6.

Responsibilities:

• Develop next generation FPGA from specification to fully functional implementation.
• Validate / Emulate FPGAs in systems.

Requirements:

• Proficient in HDL (VHDL/verilog HDL) entry and simulation.
• Proficient in FPGA timing closure/area optimization techniques.
• Experience of working with 1G/10G Ethernet MAC and PCS layers and interfaces (XGMII, XAUI, XSBI).
• Experience of working with High Density FPGAs - Altera (preferred), Xilinx Virtex.
• Experience of working with High Speed Serdes (LVDS channel, PLL) and optical modules (SFP, XFP, SFP+).
• Good working knowledge of Ethernet II, 802.3, 802.2 LLC SAP/SNAP, VLAN, MPLS, IPv4/IPv6, TCP/UDP protocols.
• Knowledge of Ethernet OAM, 802.1ag, 802.3ah, Y.1731, SyncE and IEEE 1588.
• 1/2/4/8/10G Fibre Channel.
• 5+ years of experience will be considered. 10 + preferred.

Job Code: SC-FPGA. Click here to apply.