Staff Hardware Engineer. (Location: San Jose, CA)

Responsibilities:

• Being the project lead - in charge of the project from concept to actual product.
• Being the Hardware design architect and interact with the Software designer in designing a product with most cost and time efficient.
• Debugging new and legacy products.
• Advice and provide solution to the designs (new and on-going).

Requirements:

• 10G to 40G design experience.
• FPGA and Board design – 10 years experience.
• Experience working on complex FPGA design – Xilinx’s Virtex-6 or Altera’s Stratix-IV or higher.
• Multi-Board system design experience – 10 years.
• High speed board level design experience – LVPECL, XAUI.
• Proficient in HDL (VHDL/verilog HDL) entry and simulation. Proficient in FPGA timing closure/area optimization techniques.
• Experience of working with 1G/10G Ethernet MAC and PCS layers and interfaces (XGMII, XAUI, XSBI).
• Experience of working with High Speed Serdes (LVDS channel, PLL) and optical modules (SFP, XFP, SFP+).
• Good working knowledge of Ethernet II, 802.3, 802.2 LLC SAP/SNAP, VLAN, MPLS, IPv4/IPv6, TCP/UDP protocols.
• Knowledge of Ethernet OAM, 802.1ag, 802.3ah, Y.1731, SyncE and IEEE 1588.
• 1/2/4/8/10G Fibre Channel.
• Minimum education: BS in Electrical / Electronics engineering or equivalent, with at least 10 years experience in Telecom industry.

Job Code: SC-STHWE. Click here to apply.